The technical field of this invention is digital device functional blocks, used generally in the area of microprocessor design and more specifically in the area of digital signal processor devices.
This invention is used by the TRANSFER CONTROLLER WITH HUB AND PORTS ARCHITECTURE of U.K. Patent Application No. 990919.6 filed Apr. 16, 1999. The transfer controller with hub and ports is a significant basic improvement in data transfer techniques in complex digital systems. This transfer controller allows for uniform implementation of port interfaces at the periphery of such systems. Some of these ports may be slow having a relatively low data throughput. Others may be relatively fast having the throughput and speed of the central processor unit. These two portions of the device are often driven by two separate clock signals. The first clock signal has a higher frequency called the core or main processor clock. The second clock signal is called the peripheral device clock.
Synchronization in the external ports interface is required for a high speed core device to interface with a relatively low speed peripheral device. Typical known art for synchronizing requests, data or any multi-bit quantity is to write the information into a register, and then synchronize a single signal into the other domain to indicate that the data is valid and stable. The data can then be read in the other clock domain. It is not desirable to synchronize all the bits of data individually. This may result in the data being corrupted. If the data is fed into synchronizers at the point at which the synchronizers sample the data, some of the data may be sampled on this cycle and some may be sampled a cycle later. When any generalized clock frequency relationship is allowed, it is also necessary to synchronize in both directions.
This invention is a data synchronous apparatus for synchronization between a first clock domain to a second clock domain asynchronous with the first clock domain. This invention is applicable generally to any digital device using two clocks in separate portions of the device. It is particularly useful for data transfers between a relatively high speed and a relatively low speed. Usually the high speed portion is the processor core and the relatively low speed portion is the input/output (I/O) devices.
This invention provides for pipelining of data between two clock domains with asynchronous clock signals. This invention uses a shallow circular first-in-first-out (FIFO) memory element with all words passed to and from a given stage under direction of pipelined synchronized control signals. This invention includes plural synchronizer stages. Each synchronizer stage includes a data register and a synchronizer circuit. The synchronizer circuit receives a first domain write request signal and supplies a second domain read ready signal responsive to the first domain write request signal and synchronous with second clock signal. A write pointer stores an indication of one of the synchronizer stages as a write stage. This write pointer enables the indicated write synchronizer stage to write first domain data to the corresponding data register upon receipt of said first domain write request signal. The write pointer thereafter increments to indicate a next synchronizer stage in a circular sequence. a read pointer stores an indication of one of the synchronizer stages as a read stage. The read pointer enables the indicated read stage to recall second domain data from the corresponding data register upon output of a corresponding second domain read ready signal in synchronization with the second clock signal. The read pointer thereafter increments to indicate the next synchronizer stage in the circular sequence. A multiplexer selects output data from the data register indicated by the read pointer. Thus plural first domain write request signals may simultaneously be in various states of synchronization with the second clock signal in corresponding ones of said synchronization stages.